1. Field of the Invention
The present invention relates to a multilayered wiring board having a stack structure multilayered by alternately stacking a plurality of resin insulation layers including a same resin insulation material as a main component and a plurality of conductor layers and without a so-called core board by sequentially forming build-up layers on both sides of the structure, and a method of manufacturing the same.
2. Description of Related Art
A semiconductor integrated circuit device (IC chip) used as a microprocessor of a computer or the like has recently become more and more rapid and multifunctional. Accordingly, the number of terminals tends to increase, and a pitch between terminals tends to be narrow. Generally, on the bottom face of the IC chip, a plurality of terminals are densely arranged in an array shape, and such a group of terminals are connected to a group of terminals on the motherboard in a flip-chip shape. However, since the pitch between terminals is significantly different between a group of terminals on the IC chip and a group of terminals on the motherboard, it is difficult to directly connect the IC chip onto the motherboard. For this reason, typically, a method is employed in which a semiconductor package is manufactured by mounting the IC chip onto the IC chip mounting wiring board, and the semiconductor package is mounted onto the motherboard.
As the IC chip mounting wiring board for structuring such a kind of package, a multilayered wiring board obtained by forming build-up layers on the front and rear surfaces of the core board is used in practice. In the multilayered wiring board, for example, a resin board (such as a glass epoxy board) obtained by impregnating resin with reinforced fiber is used as a core board. In addition, build-up layers are formed by alternately stacking resin insulation layers and conductor layers on the front and rear surfaces of the core board utilizing the rigidity of the core board. That is, in the multilayered wiring board, the core board has a reinforcing function and is formed to have a significantly larger thickness in comparison with the build-up layer. In addition, the wiring (specifically, a through-hole conductor or the like) for facilitating interconnection between the build-up layers formed on the front and rear surfaces is formed through the core board.
On the other hand, as semiconductor integrated circuit devices have recently become faster and faster, the signal frequency used may become a high frequency band. In this case, the wiring passing through the core board contributes to a large inductance, which is related to the occurrence of high frequency signal transmission loss or circuit malfunction thus hindering high speed operation. In order to address such problems, it has been proposed to design a multilayered wiring board without the core board (e.g., refer to Patent Documents 1 and 2). In this multilayered wiring board described in Patent Documents 1 and 2, the entire wiring length is shortened by omitting the core board which has a relatively large thickness. Therefore, it is possible to reduce high frequency signal transmission loss and operate the semiconductor integrated circuit devices at a high speed.
FIGS. 17 and 18 illustrate specific examples of the wiring boards 100A and 100B disclosed in Patent Document 1. In the wiring boards 100A and 100B, solder resists 104 and 105 are formed on both sides of the insulation layer 103 having a wiring line 101, a via conductor 102, or the like, and an opening 106 for exposing the IC chip connection wiring line 101 is provided in the solder resist 104. In addition, an opening 107 is also formed in the lower side solder resist 105, and a connection terminal 108 to the motherboard or the like is formed inside the opening 107.
In the wiring board 100A of FIG. 17, the connecting terminal 108 is embedded (buried) in the solder resist 105 side, and the connecting terminal 108 and the solder resist 105 having nearly the same thickness. Meanwhile, in the wiring board 100B of FIG. 18, the connecting terminal 108 is embedded (buried) in the insulation layer 103, and the outer circumference portion of the terminal outer surface 108a is covered by the solder resist 105. In addition, in the wiring board of Patent Document 2, the connecting terminal of the IC chip is embedded (buried) in the insulation layer side, and the outer circumference portion of the terminal outer surface is covered by the solder resist.